Signal integrity is not optional, even at low speeds

Your SPI bus runs at 10 MHz.

That's slow, right? No signal integrity concerns?

Wrong. At 10 MHz with sharp edges, your signal has harmonic content well into the hundreds of megahertz, and your PCB traces are antennas whether you planned them that way or not.

Why slow signals have fast edges

Signal integrity is about edge rate, not clock frequency. The clock sets how often a signal switches. The edge sets how fast it switches, and the edge is what the trace responds to.

Modern CMOS drivers have sub-nanosecond edges regardless of clock speed. The output stage doesn't know what clock rate you configured. It switches as fast as it was built to.

So a 10 MHz SPI clock with 1 ns edges has significant energy at 300 MHz and above. At those frequencies a trace that looks short on the layout is no longer electrically short, and it starts to behave like a transmission line and an antenna.

Where low-speed problems show up

• Ringing on SPI and I2C lines that causes double-clocking. An unterminated clock line overshoots and rings on every edge. If the ring crosses the receiver's input threshold twice, the receiver counts two clock edges where you sent one, and every bit after it lands in the wrong place.
• Crosstalk between parallel traces that corrupts data. Two traces running side by side for a long stretch couple into each other. A fast edge on one becomes a glitch on its neighbor, and if the neighbor is a clock or a chip select, that glitch becomes data.
• Ground bounce on multi-bit buses. When many outputs switch at once, their combined return current through a shared ground path lifts the local ground for a moment. Every signal referenced to that ground moves with it, including the ones that didn't switch.
• EMI failures caused by unterminated traces acting as antennas. The harmonics of those fast edges radiate. This is often where a slow design first meets signal integrity: in the EMC chamber, as a peak at a frequency nobody on the team thought the product used.

None of these look like a layout problem when they happen. They look like a firmware bug: an intermittent CRC error, a sensor that occasionally reads garbage, a bus that locks up once a day. The first suspect is usually the code, and time goes into it before anyone puts a scope probe on the clock line.

Practical signal integrity for non-RF engineers

You don't need a field solver to avoid most of this. Four habits do most of the work:

1. Route critical signals over continuous ground planes, always. Return current flows in the plane directly under the trace. Cut the plane with a split or a slot and the return current detours around it, the loop gets larger, and the loop is what radiates and picks up noise.
2. Use series termination resistors. A small resistor at the driver, sized so the driver's output impedance plus the resistor roughly matches the trace impedance, damps the reflection that causes ringing. Simple, cheap and effective, and it costs one footprint per line if you plan for it before layout.
3. Keep fast traces short and avoid vias where you can. Every via is a discontinuity, and every extra centimeter is more antenna. Place the parts that talk to each other close together and the routing follows.
4. Separate analog and digital domains with intentional return current paths. Decide where digital return current flows before you route, and keep it out from under the sensitive analog front end. A ground strategy you designed beats one the copper pour chose for you.

Check it before layout, not after the chamber

At the schematic stage, most of this costs almost nothing: a footprint for a series resistor, a stackup with a solid ground plane, a placement that keeps the clock short.

Once boards are built, the same fixes mean a respin. After a failed EMC test, they mean a respin and another round at the test lab.

The useful question in a layout review isn't how fast the clock is. It's how fast the edges are, where the return current goes, and how long the longest unterminated trace is.