Power architecture: the decision that constrains everything

Your power architecture is the one decision that touches everything in your product: performance, thermal, EMI, battery life, cost, regulatory compliance, and reliability.

Get it wrong early, and every other decision gets harder.

Power is architecture, not a subsystem

It's tempting to treat power as plumbing: pick a regulator for each voltage and move on. But every rail, every regulator and every converter affects signal integrity and EMI. A switching regulator is a noise source, and it often sits on the same board as your most sensitive measurement.

Power sequencing requirements cascade through the entire system. The order in which rails come up and go down constrains your processor, your peripherals, and the firmware that has to manage them.

And thermal management is primarily a power management problem. Every watt your conversion stages waste becomes heat that has to get out of the enclosure.

Four mistakes that show up late

• LDOs where switchers are needed. A linear regulator turns the full voltage drop times the load current into heat. On an open bench that's a warm part. In an enclosed product it can be the reason the product overheats.
• No load-step analysis. When a high-current peripheral switches on, the rail droops. If nobody analyzed that transient, the first sign is a reset that only happens under load.
• Single points of failure with no protection or monitoring. One power path, nothing to limit a fault, and no way to see a rail in trouble before the product stops.
• Ignoring input transients. Hot-plug, load dump and ESD on the power pins are what real cables and real connectors deliver. A design that has only ever seen a bench supply hasn't met them yet.

The number on the datasheet is not the loss

The same blind spot shows up in parts selection. Take the inductor in a buck converter. The number everyone designs around is DCR, the winding's DC resistance. At DC, it's the whole story.

Your converter doesn't run at DC.

At switching frequency the winding sees skin effect and proximity effect, the air gap throws a fringing field straight into the copper, and the core adds loss of its own. Proximity effect alone can raise effective winding resistance by two to five times at typical 100 to 500 kHz buck operating points.

So I don't size magnetics off DCR. I pull the AC resistance at the actual switching frequency, add the core loss, run it against the real ripple current, and only then trust the efficiency curve.

It matters because an 8 °C unmodeled rise can eat most of your thermal margin in a sealed enclosure, and that's the gap between a passing reliability test and a field return. Catching it in simulation costs an afternoon. Catching it in production costs a board respin, a new inductor footprint, and a thermal re-qualification.

A useful tell: if the inductor is the hottest single component on the board, you are almost certainly under-modeling AC loss, not under-sizing saturation current.

The power architecture checklist

Before layout, not after the first brownout:

1. Map every rail. Voltage, current, noise sensitivity, and sequencing requirements.
2. Choose a topology per rail. LDO, buck, boost or SEPIC, chosen on efficiency and noise.
3. Analyze load steps and transient response. Do it before layout, while a fix is still a schematic change.
4. Plan the thermal path for every converter. Use real loss numbers, including AC winding loss and core loss, not DCR alone.

None of this takes long at the start. Power is the decision that's expensive to unwind once the schematic is frozen.